"Power & variability test chip architecture and 45nm-generation ..."

R. Venkatraman et al. (2009)

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DOI: 10.1109/ISQED.2009.4810265

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh:
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. ISQED 2009: 27-32

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