"An Effective Timing-Driven Detailed Placement Algorithm for FPGAs."

Shounak Dhar et al. (2017)

> Home

Details and statistics

DOI: 10.1145/3036669.3036682

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ispd/DharIASRP17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ispd/DharIASRP17
Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan:
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD 2017: 151-157

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.