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2020 – today
- 2020
[c16]Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer
, David Z. Pan:
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC 2020: 26-31
2010 – 2019
- 2019
- [c15]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
A shape-driven spreading algorithm using linear programming for global placement. ASP-DAC 2019: 563-568 - [c14]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
FPGA Accelerated FPGA Placement. FPL 2019: 404-410 - [c13]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
FPGA-Accelerated Spreading for Global Placement. HPEC 2019: 1-7 - 2017
- [c12]Love Singhal, Mahesh A. Iyer, Saurabh N. Adya:
LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. DAC 2017: 30:1-30:6 - [c11]Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan:
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD 2017: 151-157 - 2016
- [c10]Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan:
Detailed placement for modern FPGAs using 2D dynamic programming. ICCAD 2016: 9 - 2011
- [c9]Shahin Golshan, Love Singhal, Eli Bozorgzadeh:
Process variation aware system-level load assignment for total energy minimization using stochastic ordering. ISQED 2011: 566-571
2000 – 2009
- 2008
- [c8]Love Singhal, Sejong Oh, Eli Bozorgzadeh:
Statistical power profile correlation for realistic thermal estimation. ASP-DAC 2008: 67-70 - [c7]Love Singhal, Sejong Oh, Eli Bozorgzadeh:
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors. CODES+ISSS 2008: 249-254 - [c6]Love Singhal, Elaheh Bozorgzadeh:
Process variation aware system-level task allocation using stochastic ordering of delay distributions. ICCAD 2008: 570-574 - 2007
- [j2]Love Singhal, Elaheh Bozorgzadeh:
Multi-layer floorplanning for reconfigurable designs. IET Comput. Digit. Tech. 1(4): 276-294 (2007) - [j1]Love Singhal, Elaheh Bozorgzadeh, David Eppstein:
Interconnect Criticality-Driven Delay Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1803-1817 (2007) - [c5]Love Singhal, Elaheh Bozorgzadeh:
Heterogeneous Floorplanner for FPGA. FCCM 2007: 311-312 - [c4]Love Singhal, Elaheh Bozorgzadeh:
Novel Multi-Layer floorplanning for Heterogeneous FPGAs. FPL 2007: 613-616 - 2006
- [c3]Love Singhal, Elaheh Bozorgzadeh:
Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. FPL 2006: 1-8 - [c2]Love Singhal, Elaheh Bozorgzadeh:
Physically-aware exploitation of component reuse in a partially reconfigurable architecture. IPDPS 2006 - 2005
- [c1]Love Singhal, Elaheh Bozorgzadeh:
Fast timing closure by interconnect criticality driven delay relaxation. ICCAD 2005: 792-797
Coauthor Index
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