"Vt balancing and device sizing towards high yield of ..."

Yu Pu et al. (2007)

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DOI: 10.1145/1283780.1283857

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
V_t balancing and device sizing towards high yield of sub-threshold static logic gates. ISLPED 2007: 355-358

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