"Transistor reordering for low power CMOS gates using an SP-BDD representation."

Alexey Glebov, David T. Blaauw, Larry G. Jones (1995)

> Home

Details and statistics

DOI: 10.1145/224081.224110

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/islped/GlebovBJ95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/islped/GlebovBJ95
Alexey Glebov, David T. Blaauw, Larry G. Jones:
Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD 1995: 161-166

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.