"A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration."

Franz Marcus Schüffny et al. (2019)

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DOI: 10.1109/ISCAS.2019.8702118

access: closed

type: Conference or Workshop Paper

metadata version: 2022-01-06

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Franz Marcus Schüffny, Sebastian Höppner, Alexander Oefelein, Christian Mayr:
A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration. ISCAS 2019: 1-5

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