"A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM."

Wei-Kai Cheng, Yen-Heng Ciou (2014)

> Home

Details and statistics

DOI: 10.3233/978-1-61499-484-8-246

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/intcompsymp/ChengC14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/intcompsymp/ChengC14
Wei-Kai Cheng, Yen-Heng Ciou:
A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM. ICS 2014: 246-253

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.