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2020 – today
- 2024
[c19]Yu-Shan Huang, Wei-Kai Cheng:
Automated Quantization Strategy on CIM. ICCE-Taiwan 2024: 223-224- [c18]Chia-Hsuan Chang, Wei-Kai Cheng:
Impact of ADC Bits on CNNs in CIM Architecture. ICCE-Taiwan 2024: 283-284 - 2023
- [c17]Yueh-Fan Lo, Wei-Kai Cheng:
Convolutional Neural Network Accelerator for Integrated Winograd and Convolution Computations. ICCE-Taiwan 2023: 305-306 - [c16]Hsin-Yi Pai, Wei-Kai Cheng:
Framework and Quantization Method Design for CIM. ICCE-Taiwan 2023: 307-308 - 2022
- [c15]Hsin-Tzu Wu, Hsin-Yi Pai, Wei-Kai Cheng:
Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM Architecture. ISOCC 2022: 163-164 - 2020
- [c14]Wei-Kai Cheng, Xiang-Yi Liu, Tsai-Yu Tsai:
Dataflow Design of Overlap-Add FFT on the Convolution Neural Networks. ICCE-TW 2020: 1-2 - [c13]Wei-Kai Cheng, Yuan-Chih Lo, Hsia-Tsung Wang:
Architecture Design of Overlap-Add FFT on the Convolution Neural Networks. ICCE-TW 2020: 1-2 - [c12]Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng:
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS 2020: 1-6
2010 – 2019
- 2019
- [c11]Wei-Kai Cheng, Chih-Shuan Wu:
Machine Learning Techniques for Building and Evaluation of Routability-driven Macro Placement. ICCE-TW 2019: 1-2 - 2018
- [c10]Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng:
An Effective Approach for Building Low-Power General Activity-Driven Clock Trees. ISOCC 2018: 13-14 - [c9]Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang:
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. ISOCC 2018: 50-51 - 2016
- [j5]Wei-Kai Cheng, Jui-Hung Hung, Yi-Hsuan Chiu:
Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2388-2397 (2016) - [j4]Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh:
Unified approach for simultaneous functional and timing ECO. IET Circuits Devices Syst. 10(6): 514-521 (2016) - [j3]Wei-Kai Cheng, Yen-Heng Ciou, Po-Yuan Shen:
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration. Microprocess. Microsystems 42: 191-199 (2016) - [c8]Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou:
Top-level activity-driven clock tree synthesis with clock skew variation considered. ISCAS 2016: 2591-2594 - 2015
- [j2]Wei-Kai Cheng, Po-Han Wu, Yi-Hsuan Chiu:
A Skew-Window based Methodology for Timing Fixing in Multiple Power Modes. J. Inf. Sci. Eng. 31(5): 1795-1812 (2015) - [c7]Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh:
A logic difference generator with spare cells consideration for ECO synthesis. ISQED 2015: 577-580 - 2014
- [c6]Wei-Kai Cheng, Yen-Heng Ciou:
A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM. ICS 2014: 246-253 - 2012
- [c5]Yi-Chun Yen, Jhih-Kai Yang, Wei-Kai Cheng:
Memory binding and layer assignment for high-level synthesis of 3D ICs. APCCAS 2012: 619-622 - [c4]Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi:
A 3D IC designs partitioning algorithm with power consideration. ISQED 2012: 137-142
1990 – 1999
- 1999
- [j1]Wei-Kai Cheng, Youn-Long Lin:
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ACM Trans. Design Autom. Electr. Syst. 4(3): 231-256 (1999) - 1998
- [c3]Wei-Kai Cheng, Youn-Long Lin:
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. ISSS 1998: 15-22 - 1995
- [c2]Wei-Kai Cheng, Youn-Long Lin:
A Transformation-Based Approach for Storage Optimization. DAC 1995: 158-163 - 1994
- [c1]Wei-Kai Cheng, Youn-Long Lin:
Code generation for a DSP processor. HLSS 1994: 82-87
Coauthor Index
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