"Synthesis of Synchronous Sequential Logic Circuits from Partial ..."

Chaiyasit Manovit, Chatchawit Aporntewan, Prabhas Chongstitvatana (1998)

> Home

Details and statistics

DOI: 10.1007/BFB0057611

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ices/ManovitAC98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ices/ManovitAC98
Chaiyasit Manovit, Chatchawit Aporntewan, Prabhas Chongstitvatana:
Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences. ICES 1998: 98-105

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.