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ORCIDChatchawit Aporntewan
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2010 – 2019
- 2016
[j4]Chatchawit Aporntewan
, Prabhas Chongstitvatana, Nachol Chaiyaratana:
Indexing Simple Graphs by Means of the Resistance Distance. IEEE Access 4: 5570-5578 (2016)- 2015
- [j3]Somsak Rakkeitwinai, Chidchanok Lursinsap, Chatchawit Aporntewan, Apiwat Mutirangura:
New feature selection for gene expression classification based on degree of class overlap in principal dimensions. Comput. Biol. Medicine 64: 292-298 (2015) - 2012
- [j2]Damrongrit Setsirichok, Theera Piroonratana, Anunchai Assawamakin, Touchpong Usavanarong, Chanin Limwongse, Waranyu Wongseree, Chatchawit Aporntewan, Nachol Chaiyaratana:
Small Ancestry Informative Marker panels for complete classification between the original four HapMap populations. Int. J. Data Min. Bioinform. 6(6): 651-674 (2012) - 2010
- [c8]Naruemon Pratanwanich, Apiwat Mutirangura, Chatchawit Aporntewan:
Mining LINE-1 Characteristics That Mediate Gene Expression. CSBio 2010: 83-93
2000 – 2009
- 2007
- [j1]Chatchawit Aporntewan, Prabhas Chongstitvatana:
Building-block Identification by Simultaneity Matrix. Soft Comput. 11(6): 541-548 (2007) - 2005
- [c7]Chatchawit Aporntewan, Prabhas Chongstitvatana:
A quantitative approach for validating the building-block hypothesis. Congress on Evolutionary Computation 2005: 1403-1409 - 2004
- [c6]Chatchawit Aporntewan, Prabhas Chongstitvatana:
Chi-Square Matrix: An Approach for Building-Block Identification. ASIAN 2004: 63-77 - [c5]Chatchawit Aporntewan, Prabhas Chongstitvatana:
Simultaneity Matrix for Solving Hierarchically Decomposable Functions. GECCO (1) 2004: 877-888 - 2003
- [c4]Chatchawit Aporntewan, Prabhas Chongstitvatana:
Building-Block Identification by Simultaneity Matrix. GECCO 2003: 1566-1567 - 2001
- [c3]Chatchawit Aporntewan, Prabhas Chongstitvatana:
A hardware implementation of the Compact Genetic Algorithm. CEC 2001: 624-629
1990 – 1999
- 1999
- [c2]Prabhas Chongstitvatana, Chatchawit Aporntewan:
Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences. Evolvable Hardware 1999: 262- - 1998
- [c1]Chaiyasit Manovit, Chatchawit Aporntewan, Prabhas Chongstitvatana:
Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences. ICES 1998: 98-105
Coauthor Index
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