"Speeding up pipelined circuits through a combination of gate sizing and ..."

Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn (1995)

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DOI: 10.1109/ICCAD.1995.480158

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn:
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD 1995: 467-470

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