"Effects of delay models on peak power estimation of VLSI sequential circuits."

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel (1997)

> Home

Details and statistics

DOI: 10.1109/ICCAD.1997.643360

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/iccad/HsiaoRP97
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccad/HsiaoRP97
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Effects of delay models on peak power estimation of VLSI sequential circuits. ICCAD 1997: 45-51

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.