"A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased ..."

Xinyu Shen et al. (2023)

> Home

Details and statistics

DOI: 10.1109/ESSCIRC59616.2023.10268691

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/esscirc/ShenZLCQLWL23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/ShenZLCQLWL23
Xinyu Shen, Zhao Zhang, Guike Li, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. ESSCIRC 2023: 257-260

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.