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"A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based ..."
Tsung-Te Liu, Chorng-Kuang Wang (2004)
- Tsung-Te Liu, Chorng-Kuang Wang:
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator. ESSCIRC 2004: 375-378
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