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2010 – 2019
- 2014
[c26]Yi-Long Yu, Fu-Chen Huang, Chorng-Kuang Wang:
A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS. VLSI-DAT 2014: 1-4- 2013
- [j9]Yu-Jie Huang, Che-Wei Huang, Tsung-Hsien Lin
, Chih-Ting Lin, Li-Guang Chen, Po-Yun Hsiao, Bi-Ru Wu, Hsiao-Ting Hsueh, Bing-Jye Kuo, Hann-Huei Tsai, Hsin-Hao Liao, Ying-Zong Juang, Chorng-Kuang Wang, Shey-Shi Lu:
A CMOS Cantilever-Based Label-Free DNA SoC With Improved Sensitivity for Hepatitis B Virus Detection. IEEE Trans. Biomed. Circuits Syst. 7(6): 820-831 (2013) - 2012
- [c25]Kun-Yin Wang, Tao-Yao Chang, Chorng-Kuang Wang:
A 1V 19.3dBm 79GHz power amplifier in 65nm CMOS. ISSCC 2012: 260-262 - [c24]Yi-Hung Lin, Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang:
I/Q imbalance compensation and channel equalization algorithm for MISO-OFDM systems. ITST 2012: 852-856 - [c23]Tzon-Tzer Lu, Hua-Chin Lee, Chao-Shiun Wang, Chorng-Kuang Wang:
A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode. VLSI-DAT 2012: 1-4 - [c22]Che-Wei Huang, Yu-Jie Huang, Pei-Wen Yen, Hsiao-Ting Hsueh, Chia-Yi Lin, Min-Cheng Chen, Chia-Hua Ho, Fu-Liang Yang, Hann-Huei Tsai, Hsin-Hao Liao, Ying-Zong Juang, Chorng-Kuang Wang, Chih-Ting Lin, Shey-Shi Lu:
A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS process. VLSIC 2012: 124-125 - 2011
- [j8]Hsi-Han Chiang, Fu-Chien Huang, Chao-Shiun Wang, Chorng-Kuang Wang:
A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique. IEEE J. Solid State Circuits 46(11): 2583-2591 (2011) - [c21]Tao-Yao Chang, Chao-Shiun Wang, Chorng-Kuang Wang:
A low power W-band PLL with 17-mW in 65-nm CMOS technology. A-SSCC 2011: 81-84 - [c20]Shu-Wei Chu, Chorng-Kuang Wang:
An 85-GHz injection-locked frequency divider with current-reuse pre-amplifier technique. A-SSCC 2011: 89-92 - 2010
- [j7]Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang:
Joint Carrier Synchronization and Equalization Algorithm for Packet-Based OFDM Systems Over the Multipath Fading Channel. IEEE Trans. Veh. Technol. 59(1): 248-260 (2010) - [c19]Ting-Yuan Chen, Yi-Hsien Lin, Chih-Feng Wu, Chorng-Kuang Wang:
Design and analysis of cost-efficient IFFT/FFT processor chip for wireless OFDM systems. APCCAS 2010: 760-763 - [c18]Tao-Yao Chang, Chao-Shiun Wang, Chorng-Kuang Wang:
A 77 GHz power amplifier using transformer-based power combiner in 90 nm CMOS. CICC 2010: 1-4 - [c17]Ming-Yeh Hsu, Chao-Shiun Wang, Chorng-Kuang Wang:
A low power high reliability dual-path noise-cancelling LNA for WSN applications. CICC 2010: 1-4
2000 – 2009
- 2009
- [j6]Chao-Shiun Wang, Juin-Wei Huang, Kun-Da Chu, Chorng-Kuang Wang:
A 60-GHz Phased Array Receiver Front-End in 0.13-mu hboxm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(10): 2341-2352 (2009) - [c16]Fang-Li Yuan, Chin-Hsien Lin, Yi-Hsien Lin, Chih-Feng Wu, Chorng-Kuang Wang:
A MIMO-OFDM digital baseband receiver design with adaptive equalization technique for IEEE 802.16 WMAN. ICASSP 2009: 617-620 - [c15]Yi-Hsien Lin, Chih-Hsien Lin, Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang:
Cost-Effective Equalization for STBC MIMO/MISO OFDM Systems over Multipath Fading Channel. VTC Fall 2009 - [c14]Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang:
Joint Carrier Synchronization and Equalization Algorithm for OFDM Systems - Closed-Loop Derivation. VTC Spring 2009 - [c13]Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang:
Joint Carrier Synchronization and Equalizaiton Algorithm for OFDM Systems - Loop-Delay Analysis and Complexity Consideration. VTC Fall 2009 - 2008
- [c12]Chao-Shiun Wang, Juin-Wei Huang, Kun-Da Chu, Chorng-Kuang Wang:
A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communications. CICC 2008: 479-482 - [c11]Shon-Hang Wen, Chao-Shiun Wang, Chorng-Kuang Wang:
A low power 20 GHz 1.5 Gb/s CMOS injection-pulling FSK modulator and frequency discriminator for 60GHz links. CICC 2008: 483-486 - [c10]Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang:
Joint Carrier Synchronization and Equalization for OFDM Systems Over Multipath Fading Channel. VTC Fall 2008: 1-5 - 2007
- [c9]Chao-Shiun Wang, Juin-Wei Huang, Shon-Hang Wen, Shih-Huang Yeh, Chorng-Kuang Wang:
A CMOS RF front-end with on-chip antenna for V-band broadband wireless communications. ESSCIRC 2007: 143-146 - 2005
- [c8]Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang:
DHT-based frequency-domain equalizer for DMT systems. EUSIPCO 2005: 1-4 - [c7]Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, Hen-Wai Tsao:
A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications. ISCAS (1) 2005: 368-371 - [c6]Chao-Shiun Wang, Wei-Chang Li, Chorng-Kuang Wang:
A multi-band multi-standard RF front-end IEEE 802.16a for IEEE 802.16a and IEEE 802.11 a/b/g applications. ISCAS (4) 2005: 3974-3977 - [c5]Ching-Chi Chang, Chorng-Kuang Wang:
High speed pilot-less sampling frequency acquisition for DMT systems. ISCAS (5) 2005: 4895-4898 - [c4]Wei-Hsiang Tseng, Ching-Chi Chang, Chorng-Kuang Wang:
Digital VLSI OFDM transceiver architecture for wireless SoC design. ISCAS (6) 2005: 5794-5797 - 2004
- [c3]Tsung-Te Liu, Chorng-Kuang Wang:
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator. ESSCIRC 2004: 375-378 - [c2]Hung-Chieh Tsai, Jyh-Yih Yeh, Wei-Hsuan Tu, Tai-Cheng Lee, Chorng-Kuang Wang:
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier. ISCAS (4) 2004: 393-396 - 2001
- [j5]Po-Chiun Huang, Yi-Huei Chen, Chorng-Kuang Wang:
A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier. IEEE J. Solid State Circuits 36(1): 135-138 (2001) - [c1]Ching-Chi Chang, Chien-Chih Lin, Muh-Tian Shiue, Chorng-Kuang Wang:
A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop. ISCAS (4) 2001: 358-361 - 2000
- [j4]Po-Chiun Huang, Yi-Huei Chen, Chorng-Kuang Wang:
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI. IEEE J. Solid State Circuits 35(10): 1474-1480 (2000)
1990 – 1999
- 1999
- [j3]Kuang-Hu Huang, Wei-Cheng Wang, Tang-Huei Yang, Chorng-Kuang Wang:
A 2-V 7.2° jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control. IEEE J. Solid State Circuits 34(10): 1373-1381 (1999) - [r1]Min-shueh Yuan, Chorng-Kuang Wang:
PLL Circuits. The VLSI Handbook 1999 - 1996
- [j2]Chorng-Kuang Wang, Po-Chiun Huang, Chen-Yi Huang:
A BiCMOS limiting amplifier for SONET OC-3. IEEE J. Solid State Circuits 31(8): 1197-1200 (1996)
1980 – 1989
- 1989
- [j1]Sui-Ping Shieh, Chorng-Kuang Wang, Rinaldo Castello, Paul R. Gray:
A scalable switched-capacitor filter implemented in 1.25- mu m technology. IEEE J. Solid State Circuits 24(1): 174-177 (1989)
Coauthor Index
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