"Synthesis of Multivalued Logical Networks for FPGA Implementations."

Stanislaw Deniziak, Mariusz Wisniewski, Karol Wieczorek (2016)

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DOI: 10.1109/DSD.2016.107

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/dsd/DeniziakWW16
Stanislaw Deniziak, Mariusz Wisniewski, Karol Wieczorek:
Synthesis of Multivalued Logical Networks for FPGA Implementations. DSD 2016: 657-660

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