"Temporal parallel simulation: A fast gate-level HDL simulation using ..."

Dusung Kim et al. (2011)

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DOI: 10.1109/DATE.2011.5763251

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang:
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE 2011: 1584-1589

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