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Journal Articles
- 2013
[j3]Dusung Kim, Maciej J. Ciesielski, Seiyang Yang:
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 845-857 (2013)- 1992
- [j2]Maciej J. Ciesielski, Seiyang Yang:
PLADE: a two-stage PLA decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 943-954 (1992) - 1991
- [j1]Seiyang Yang, Maciej J. Ciesielski:
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1): 4-12 (1991)
Conference and Workshop Papers
- 2014
- [c8]Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim:
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy. DATE 2014: 1-3 - 2011
- [c7]Dusung Kim, Maciej J. Ciesielski, Seiyang Yang:
A new distributed event-driven gate-level HDL simulation by accurate prediction. DATE 2011: 547-550 - [c6]Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang:
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE 2011: 1584-1589 - 2008
- [c5]Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang:
A fast two-pass HDL simulation with on-demand dump. ASP-DAC 2008: 422-427 - [c4]Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang:
Temporal parallel gate-level timing simulation. HLDVT 2008: 111-116 - [c3]Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang:
Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491 - 2004
- [c2]Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski:
A new state assignment technique for testing and low power. DAC 2004: 510-513 - 1989
- [c1]Seiyang Yang, Maciej J. Ciesielski:
PLA decomposition with generalized decoders. ICCAD 1989: 312-315
Coauthor Index
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