"Logic Design for On-Chip Test Clock Generation - Implementation Details ..."

Matthias Beck et al. (2005)

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DOI: 10.1109/DATE.2005.199

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. DATE 2005: 56-61

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