"Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis ..."

Ivo Bolsens et al. (1989)

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DOI: 10.1145/74382.74468

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man:
Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. DAC 1989: 513-518

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