"A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation ..."

Koichiro Minami et al. (2001)

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DOI: 10.1109/CICC.2001.929758

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-10

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Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina:
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC 2001: 213-216

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