"A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with ..."

Shuai Chen et al. (2013)

> Home

Details and statistics

DOI: 10.1109/CICC.2013.6658549

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cicc/ChenLYYHC13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cicc/ChenLYYHC13
Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang:
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. CICC 2013: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.