"A Unified Interconnects Testing Scheme for 3D Integrated Circuits."

Chih-Yun Pai et al. (2011)

> Home

Details and statistics

DOI: 10.1109/ATS.2011.38

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/ats/PaiGCCL11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ats/PaiGCCL11
Chih-Yun Pai, Ruei-Ting Gu, Bo-Chuan Cheng, Liang-Bi Chen, Katherine Shu-Min Li:
A Unified Interconnects Testing Scheme for 3D Integrated Circuits. Asian Test Symposium 2011: 195-200

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.