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2010 – 2019
- 2017
[j1]Katherine Shu-Min Li
, Sying-Jyan Wang, Ruei-Ting Gu, Bo-Chuan Cheng:
Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. IEEE Des. Test 34(6): 77-83 (2017)- 2016
- [c6]Liang-Bi Chen, Bo-Chuan Cheng, You-Chiun Wang, Katherine Shu-Min Li, Jing-Jou Tang:
An efficient fault tolerance path finding algorithm for improving the robustness of multichannel wireless mesh networks. ICCE 2016: 524-525 - 2014
- [c5]Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng:
Optimized Pre-bond Test Methodology for Silicon Interposer Testing. ATS 2014: 13-18 - 2013
- [c4]Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu:
A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. Asian Test Symposium 2013: 159-164 - 2012
- [c3]Bo-Chuan Cheng, Katherine Shu-Min Li, Sying-Jyan Wang:
De Bruijn graph-based communication modeling for fault tolerance in smart grids. APCCAS 2012: 623-626 - 2011
- [c2]Chih-Yun Pai, Ruei-Ting Gu, Bo-Chuan Cheng, Liang-Bi Chen, Katherine Shu-Min Li:
A Unified Interconnects Testing Scheme for 3D Integrated Circuits. Asian Test Symposium 2011: 195-200 - [c1]Yi-Xue Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li:
Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits. SoCC 2011: 296-301
Coauthor Index
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