"A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x ..."

Kasho Yamamoto et al. (2021)

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DOI: 10.1109/A-SSCC53895.2021.9634769

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type: Conference or Workshop Paper

metadata version: 2021-12-21

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Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka:
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. A-SSCC 2021: 1-3

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