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Chihiro Yoshimura
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2020 – today
- 2024
- [j7]Shunsuke Minusa, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno:
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale. IEEE Access 12: 122929-122941 (2024) - [j6]Tadayuki Matsumura, Kanako Esaki, Shao Yang, Chihiro Yoshimura, Hiroyuki Mizuno:
Active Inference With Empathy Mechanism for Socially Behaved Artificial Agents in Diverse Situations. Artif. Life 30(2): 277-297 (2024) - [i1]Shunsuke Minusa, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno:
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale. CoRR abs/2403.10136 (2024) - 2023
- [c14]Ryuji Ukai, Chihiro Yoshimura, Hiroyuki Mizuno:
Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers. candar 2023: 196-202 - [c13]Kanako Esaki, Tadayuki Matsumura, Shunsuke Minusa, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno:
Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference. IWAI 2023: 14-28 - 2022
- [c12]Kanako Esaki, Tadayuki Matsumura, Chihiro Yoshimura, Hiroyuki Mizuno:
Extended-Self Recognition for Autonomous Agent Based on Controllability and Predictability. SSCI 2022: 1036-1043 - 2021
- [c11]Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka:
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. A-SSCC 2021: 1-3 - [c10]Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka:
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. ISSCC 2021: 64-66 - 2020
- [j5]Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. IEEE J. Solid State Circuits 55(1): 145-156 (2020) - [c9]Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka:
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. ASP-DAC 2020: 673-678
2010 – 2019
- 2019
- [c8]Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto:
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. CICC 2019: 1-8 - [c7]Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. ISSCC 2019: 52-54 - [c6]Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka:
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. VLSI Circuits 2019: 148- - 2017
- [j4]Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka:
Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing. Int. J. Netw. Comput. 7(2): 154-172 (2017) - 2016
- [j3]Risa Shiroyama, Chihiro Yoshimura:
Assessing bluegill (Lepomis macrochirus) habitat suitability using partial dependence function combined with classification approaches. Ecol. Informatics 35: 9-18 (2016) - [j2]Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. Int. J. Netw. Comput. 6(2): 195-211 (2016) - [j1]Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. IEEE J. Solid State Circuits 51(1): 303-309 (2016) - [c5]Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka:
FPGA-based Annealing Processor for Ising Model. CANDAR 2016: 436-442 - [c4]Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Masanao Yamaoka:
Computing architecture to perform approximated simulated annealing for Ising models. ICRC 2016: 1-8 - 2015
- [c3]Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. CANDAR 2015: 542-546 - [c2]Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. ISSCC 2015: 1-3 - 2013
- [c1]Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, Hiroyuki Mizuno:
Spatial computing architecture using randomness of memory cell stability under voltage control. ECCTD 2013: 1-4
Coauthor Index
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