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ORCIDOleg Maslennikov
Person information
- affiliation: Technical University of Koszalin, Poland
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2020 – today
- 2020
[j2]Mechislav M. Pugavko
, Oleg Maslennikov, Vladimir I. Nekorkin:
Dynamics of spiking map-based neural networks in problems of supervised learning. Commun. Nonlinear Sci. Numer. Simul. 90: 105399 (2020)
2010 – 2019
- 2016
- [c18]Oleg Maslennikov, Igor Komarov:
Efficiency metrics for flocking with implicit leadership. FRUCT 2016: 206-211 - [c17]Igor A. Zikratov, Oleg Maslennikov, Ilya Lebedev, Aleksandr Ometov, Sergey Andreev:
Dynamic Trust Management Framework for Robotic Multi-Agent Systems. NEW2AN 2016: 339-348 - 2015
- [j1]Oleg Maslennikov, Vladimir I. Nekorkin:
Evolving dynamical networks with transient cluster activity. Commun. Nonlinear Sci. Numer. Simul. 23(Issues): 10-16 (2015)
2000 – 2009
- 2009
- [c16]Piotr Ratuszniak, Oleg Maslennikow:
New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices. IMCSIT 2009: 771-777 - [c15]Anatolij Sergiyenko, Oleg Maslennikow, Piotr Ratuszniak, Natalia Maslennikowa, Adam Tomas:
Application Specific Processors for the Autoregressive Signal Analysis. PPAM (1) 2009: 80-86 - 2007
- [c14]Oleg Maslennikow, Volodymyr Lepekha, Anatoli Sergyienko, Adam Tomas, Roman Wyrzykowski:
Parallel Implementation of Cholesky LLT-Algorithm in FPGA-Based Processor. PPAM 2007: 137-147 - 2006
- [c13]Oleg Maslennikow, Anatoli Sergyienko:
Mapping DSP Algorithms into FPGA. PARELEC 2006: 208-213 - 2005
- [c12]Oleg Maslennikow, Volodymyr Lepekha, Anatoli Sergyienko:
FPGA Implementation of the Conjugate Gradient Method. PPAM 2005: 526-533 - 2003
- [c11]Oleg Maslennikow, Juri Shevtshenko, Anatoli Sergyienko:
Configurable Microprocessor Array for DSP Applications. PPAM 2003: 36-41 - 2002
- [c10]Oleg Maslennikow, Piotr Pawlowski, Przemyslaw Soltan, Robert Berezowski:
Current-mode digital gates and circuits: concept, design and verification. ICECS 2002: 623-626 - [c9]Oleg Maslennikov, Juri Shevtshenko, Anatoli Sergyienko:
Configurable Microcontroller Array. PARELEC 2002: 47-49 - 2001
- [c8]Oleg Maslennikov:
Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units. PPAM 2001: 272-279 - [c7]Anatoli Sergyienko, Oleg Maslennikov:
Implementation of Givens QR-Decomposition in FPGA. PPAM 2001: 458-465
1990 – 1999
- 1998
- [c6]Anatoli Sergyienko, Juri Kanevski, Oleg Maslennikov, Roman Wyrzykowski:
A Method for Mapping DSP Algorithms into Application Specific Structures. EUROMICRO 1998: 10365- - [c5]Oleg Maslennikow, Juri Kaniewski, Roman Wyrzykowski:
Fault Tolerant QR-Decomposition Algorithm and Its Parallel Implementation. Euro-Par 1998: 798-803 - 1997
- [c4]Roman Wyrzykowski, Juri Kanevski, Oleg Maslennikov:
A new orthogonal version of the Gauss-Jordan algorithm and its parallel implementation. PDP 1997: 445-452 - 1996
- [c3]Juri Kanevski, Oleg Maslennikov, Anatoli Sergyienko:
Processor Array for Signal Computing and Numerical Applications. Parcella 1996: 47-58 - [c2]Juri Kanevski, Oleg Maslennikov, Roman Wyrzykowski:
Algorithm-Based Fault Tolerant Solution of Linear Systems on Processor Arrays. Parcella 1996: 165-173 - 1995
- [c1]Juri Kanevski, Oleg Maslennikov, Roman Wyrzykowski:
VLSI Implementation of Linear Algebraic Operations Based on the Orthogonal Fadddeev Algorithm. PARCO 1995: 641-644
Coauthor Index
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