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2020 – today
- 2022
[c10]Bruno Vaz
, Vítor Bernardes, Álvaro Figueira:
On Creation of Synthetic Samples from GANs for Fake News Identification Algorithms. WorldCIST (3) 2022: 316-326
2010 – 2019
- 2018
- [c9]Bruno Vaz, Bob Verbruggen, Christophe Erdmann, Diarmuid Collins, John McGrath, Ali Boumaalif, Edward Cullen, Darragh Walsh, Alonso Morgado, Conrado Mesadri, Brian Long, Rajitha Pathepuram, Ronnie De La Torre, Alvin Manlapat, Georgios Karyotis, Dimitris Tsaliagos, Patrick Lynch, Peng Lim, Daire Breathnach, Brendan Farley:
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET. VLSI Circuits 2018: 99-100 - [c8]Christophe Erdmann, Bob Verbruggen, Bruno Vaz, Roberto Pelliconi, John McGrath, Ryan Kinnerk, Ronnie De La Torre, John O'Dwyer, Patrick Lynch, Padraig Kelly, Peng Lim, Daire Breathnach, Brendan Farley:
A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC. VLSI Circuits 2018: 219-220 - 2017
- [c7]Brendan Farley, Christophe Erdmann, Bruno Vaz, John McGrath, Edward Cullen, Bob Verbruggen, Roberto Pelliconi, Daire Breathnach, Peng Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, David Melinn, Kwee Peng Yap, Liam Madden:
A programmable RFSoC in 16nm FinFET technology for wideband communications. A-SSCC 2017: 1-4 - [c6]Bruno Vaz, Adrian Lynam, Bob Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, Ronnie De La Torre, Alvin Manlapat, Daire Breathnach, Christophe Erdmann, Brendan Farley:
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. ISSCC 2017: 276-277
2000 – 2009
- 2006
- [c5]João Goes, Bruno Vaz, Rui Monteiro, Nuno Paulino:
A 0.9V ΔΣ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase Technique. ISSCC 2006: 191-200 - 2005
- [j1]João Goes, Nuno Paulino, H. Pinto, Rui Monteiro, Bruno Vaz, Adolfo Steiger-Garção:
Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(12): 2595-2604 (2005) - [c4]João Goes, Bruno Vaz, Nuno Paulino, H. Pinto, Rui Monteiro, Adolfo Steiger-Garção:
Switched-capacitor circuits using a single-phase scheme. ISCAS (4) 2005: 3123-3126 - [c3]Bruno Vaz, João Goes, R. Piloto, J. Neto, Rui Monteiro, Nuno Paulino:
A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing. ISCAS (4) 2005: 4074-4077 - 2003
- [c2]Romero Tavares, Bruno Vaz, João Goes, Nuno F. Paulino, Adolfo Steiger-Garção:
Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance. ISCAS (1) 2003: 197-200 - 2002
- [c1]Bruno Vaz, Nuno F. Paulino, João Goes, R. Costa, Romero Tavares, Adolfo Steiger-Garção:
Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion. ISCAS (1) 2002: 921-924
Coauthor Index
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