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2020 – today
- 2023
[j4]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability. IEICE Trans. Inf. Syst. 106(3): 337-348 (2023)- 2022
- [j3]Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA. Int. J. Netw. Comput. 12(2): 425-445 (2022) - [c7]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. HEART 2022: 1-9 - 2021
- [j2]Koki Honda, Kaijie Wei
, Masatoshi Arai, Hideharu Amano:
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst. 104-D(12): 2048-2056 (2021) - [c6]Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. CANDAR (Workshops) 2021: 297-300 - 2020
- [c5]Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano:
CLAHE implementation on a low-end FPGA board by high-level synthesis. CANDAR (Workshops) 2020: 282-285
2010 – 2019
- 2011
- [c4]Masato Tsukada, Chisato Funayama, Masatoshi Arai, Charles Dubout:
Face Image Enhancement Taking into Account Lighting Behavior on a Face. CAIP (2) 2011: 479-488 - 2010
- [j1]Takeharu Goji Etoh, Son Dao Vu Truong, Toshiaki Koike-Akino, Toshiro Akino, Kenji Nishi, Masatoshi Kureta, Masatoshi Arai:
Ultra-High-Speed Image Signal Accumulation Sensor. Sensors 10(4): 4100-4113 (2010)
2000 – 2009
- 2007
- [c3]Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka:
Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA. CIT 2007: 567-572 - [c2]Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka:
A High Speed License Plate Recognition System on an FPGA. FPL 2007: 554-557
1990 – 1999
- 1993
- [c1]Masatoshi Arai, Tohru Nakagawa, Hajime Kitagawa:
A neural inverse function for automatic test pattern generation using strictly digital neural networks. VTS 1993: 238-243
Coauthor Index
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