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2020 – today
- 2022
[c7]Fatma Jebali, Oumaima Matoussi, Arief Wicaksana, Amir Charif, Lilia Zaourar:
Decoupling processor and memory hierarchy simulators for efficient design space exploration. DroneSE/RAPIDO@HiPEAC 2022: 47-52- 2021
- [j1]Arif Sasongko
, I. M. Narendra Kumara, Arief Wicaksana, Frédéric Rousseau, Olivier Muller:
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. ACM Trans. Reconfigurable Technol. Syst. 14(3): 14:1-14:25 (2021) - 2020
- [c6]Cinzia Bernardeschi, Andrea Domenici, Maurizio Palmieri, Sergio Saponara, Tanguy Sassolas, Arief Wicaksana, Lilia Zaourar:
Cross-level Co-simulation and Verification of an Automatic Transmission Control on Embedded Processor. SEFM 2020: 263-279
2010 – 2019
- 2019
- [c5]Arief Wicaksana, Amir Charif, Caaliph Andriamisaina, Nicolas Ventroux:
Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design. DASIP 2019: 35-40 - 2017
- [c4]Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau:
Prototyping dynamic task migration on heterogeneous reconfigurable systems. RSP 2017: 16-22 - 2016
- [c3]Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau:
Demonstration of a context-switch method for heterogeneous reconfigurable systems. FPL 2016: 1 - [c2]Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau, Arif Sasongko:
On-board non-regression test of HLS tools targeting FPGA. RSP 2016: 41-47 - [i2]Arief Wicaksana, Arif Sasongko:
Fast and reconfigurable packet classification engine in FPGA-based firewall. CoRR abs/1611.06078 (2016) - [i1]Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau:
Demonstration of a context-switch method for heterogeneous reconfigurable systems. CoRR abs/1611.06796 (2016) - 2011
- [c1]Arief Wicaksana, Arif Sasongko:
Fast and reconfigurable packet classification engine in FPGA-based firewall. ICEEI 2011: 1-6
Coauthor Index
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