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ORCIDKenji Shimazaki
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2010 – 2019
- 2010
[j5]Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto
:
Gate Delay Estimation in STA under Dynamic Power Supply Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2447-2455 (2010)- [c9]Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto:
Gate delay estimation in STA under dynamic power supply noise. ASP-DAC 2010: 775-780
2000 – 2009
- 2009
- [c8]Kenji Shimazaki, Takaaki Okumura:
A minimum decap allocation technique based on simultaneous switching for nanoscale SoC. CICC 2009: 21-24 - 2006
- [j4]Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa:
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Trans. Electron. 89-C(11): 1535-1543 (2006) - 2005
- [j3]Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa:
Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. IEICE Trans. Electron. 88-C(4): 589-596 (2005) - [j2]Hiroyuki Tsujikawa, Kenji Shimazaki, Shozo Hirano, Kazuhiro Sato, Masanori Hirofuji, Junichi Shimada, Mitsumi Ito, Kiyohito Mukai:
Power-Supply Noise Reduction with Design for Manufacturability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3421-3428 (2005) - [c7]Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa:
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. CICC 2005: 31-34 - [c6]Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata:
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. CICC 2005: 35-38 - 2004
- [c5]Shen Lin, Makoto Nagata, Kenji Shimazaki, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang:
Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. CICC 2004: 509-512 - 2003
- [j1]Hiroyuki Tsujikawa, Shozo Hirano, Kenji Shimazaki:
A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2974-2982 (2003) - [c4]Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto:
A substrate noise analysis methodology for large-scale mixed-signal ICs. CICC 2003: 369-372 - 2002
- [c3]Hiroyulu Tsujikawa, Kenji Shimazaki, Shozo Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno:
A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification. CICC 2002: 299-302 - [c2]Kenji Shimazaki, Shouzou Hirano, Hiroyuki Tsujikawa:
An EMI-Noise Analysis on LSI Design with Impedance Estimation. ISQED 2002: 169-174 - 2000
- [c1]Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano:
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator. ISQED 2000: 129-136
Coauthor Index
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