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Shang-E Tai

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1990 – 1999

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1995
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Shang-E Tai, Debashis Bhattacharya:
A three-stage partial scan design method to ease ATPG. J. Electron. Test. 7(1-2): 95-104 (1995)
1994
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Shang-E Tai, Debashis Bhattacharya:
A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. VLSI Design 1994: 101-106
1993
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Shang-E Tai, Debashis Bhattacharya:
Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. ICCD 1993: 564-567

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