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ORCIDHideo Wada
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2010 – 2019
- 2013
[j2]Kiyoshi Nagata, Fidel R. Nemenzo, Hideo Wada:
Mass formula and structure of self-dual codes over Z2s. Des. Codes Cryptogr. 67(3): 293-316 (2013)
2000 – 2009
- 2009
- [j1]Kiyoshi Nagata, Fidel R. Nemenzo, Hideo Wada:
The number of self-dual codes over Zp3{Z_{p^3}}. Des. Codes Cryptogr. 50(3): 291-303 (2009) - [c8]Kiyoshi Nagata, Fidel R. Nemenzo, Hideo Wada:
On Self-dual Codes over Z16. AAECC 2009: 107-116
1990 – 1999
- 1997
- [c7]Hiroaki Fujii, Yoshiko Yasuda, Hideya Akashi, Yasuhiro Inagami, Makoto Koga, Osamu Ishihara, Masamori Kashiyama, Hideo Wada, Tsutomu Sumimoto:
Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System. IPPS 1997: 233-241 - [c6]Yoshiko Yasuda, Hiroaki Fujii, Hideya Akashi, Yasuhiro Inagami, Teruo Tanaka, Junji Nakagoshi, Hideo Wada, Tsutomu Sumimoto:
Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201. IPPS 1997: 346-352 - 1993
- [c5]Hiroshi Nakamura
, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita:
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. International Conference on Supercomputing 1993: 298-307
1980 – 1989
- 1989
- [c4]Hideo Wada, Tadaaki Isobe, Masao Furukawa, Shun Kawabe:
High-speed storage control schemes of HITACHI supercomputer S-820 system. ICS 1989: 341-350 - [c3]Michihiro Hirai, Shun Kawabe, Hideo Wada:
An Overview of the HITACHI S-820 Supercomputer System. Supercomputer 1989: 56-80 - 1988
- [c2]Hideo Wada, Koichi Ishii, Shigeko Yazawa, Shun Kawabe:
High-Speed Vector Instruction Execution Schemes of HITACHI Supercomputer S-820 System. ICPP (1) 1988: 291-298 - [c1]Hideo Wada, K. Ishil, Masakazu Fukagawa, H. Murayama, Shun Kawabe:
High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system. ICS 1988: 196-206
Coauthor Index
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