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ORCIDKisaburo Nakazawa
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1990 – 1999
- 1999
[j3]Kisaburo Nakazawa, Hiroshi Nakamura
, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita:
CP-PACS: A massively parallel processor at the University of Tsukuba. Parallel Comput. 25(13-14): 1635-1661 (1999)- 1997
- [c8]Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa:
Advanced processor design using hardware description language AIDL. ASP-DAC 1997: 387-390 - [c7]Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa:
CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations. International Conference on Supercomputing 1997: 108-115 - 1996
- [j2]Taisuke Boku, Kisaburo Nakazawa, Hiroshi Nakamura, Takeshi Sone, Takeshi Mishima, Ken'ichi Itakura:
Adaptive routing technique on hypercrossbar network and its evaluation. Syst. Comput. Jpn. 27(4): 55-64 (1996) - 1995
- [c6]Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa:
A superscalar RISC processor with pseudo vector processing feature. ICCD 1995: 102-109 - 1994
- [c5]Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita:
Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. HICSS (1) 1994: 368-377 - 1993
- [c4]Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita:
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. International Conference on Supercomputing 1993: 298-307 - 1992
- [c3]Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe:
Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. SC 1992: 642-651
1960 – 1969
- 1964
- [c2]Kenro Murata, Kisaburo Nakazawa:
Very high speed serial and serial-parallel computers HITAC 5020 and 5020E. AFIPS Fall Joint Computing Conference (1) 1964: 187-203 - 1962
- [c1]S. Takahashi, Kisaburo Nakazawa, Kenro Murata, Osamu Ishii:
A Tunnel-Diode High-Speed Memory. IFIP Congress 1962: 603-607 - 1960
- [j1]Eiichi Goto, Kenro Murata, Kisaburo Nakazawa, Keisuke Nakagawa, Tohru Moto-Oka, Yasushi Miatsu-Oka, Yoshihiro Ishibashi, Haruhisa Ishida, Takashi Soma, Eiiti Wada:
Esaki Diode High-Speed Logical Circuits. IRE Trans. Electron. Comput. 9(1): 25-29 (1960)
Coauthor Index
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