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ORCIDFei Li 0003
Person information
- affiliation: Microsemi Corporation, Aliso Viejo, CA, USA
- affiliation: Actel Corporation, Mountain View, CA, USA
- affiliation: University of California, Los Angeles, CA, USA
Other persons with the same name
- Fei Li — disambiguation page
- Fei Li 0001
![[0000-0003-0879-1401]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-0879-1401")
— George Mason University, Fairfax, VA, USA - Fei Li 0002 — Siemens AG, Vienna, Austria (and 1 more)
- Fei Li 0004 — Beijing Institute of Radiation Medicine, Beijing, China (and 1 more)
- Fei Li 0005 — Fujitsu Research and Development Center Co., Beijing, China
- Fei Li 0006 — Guangzhou University, Guangzhou, China (and 1 more)
- Fei Li 0007 — Wuhan University, Wuhan, China
- Fei Li 0008 — Zhejiang University, State Key Lab of Fluid Power Transmission and Control, Hangzhou, China
- Fei Li 0009 — Tianjin University, School of Electrical Engineering and Automation, Tianjin, China
- Fei Li 0010 — Anhui University of Finance and Economics, Bengbu City, China
- Fei Li 0011 — Northwestern Polytechnical University, School of Computer Science, Xi'an, China
- Fei Li 0012 — City University London, School of Engineering and Mathematical Sciences, London, UK
- Fei Li 0013 — Virginia Tech, Blacksburg, VA, USA
- Fei Li 0014 — Nanjing University of Posts and Telecommunications, College of Telecommunication and Information Engineering, China
- Fei Li 0015 — A*STAR, Data Storage Institute, Singapore (and 1 more)
- Fei Li 0016 — Shandong University, School of Information Science and Engineering, Jinan, China
- Fei Li 0017 — Huazhong University of Science and Technology, Department of Electronics and Information Engineering, Wuhan, China
- Fei Li 0018 — Shenyang Aerospace University, Liaoning, China (and 1 more)
- Fei Li 0019 — Anhui University of Technology, Department of Electrical and Information Engineering, Maanshan, China (and 1 more)
- Fei Li 0020 — Beijing University of Posts and Telecommunications, China
- Fei Li 0021 — Wuhan University, Key Laboratory of Aerospace Information Security and Trusted Computing, Wuhan, China
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2010 – 2019
- 2011
[c15]Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner:
A 65nm flash-based FPGA fabric optimized for low cost and power. FPGA 2011: 87-96- 2010
- [j5]Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng:
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1709-1722 (2010)
2000 – 2009
- 2007
- [j4]Fei Li, Yan Lin, Lei He:
Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 752-764 (2007) - [j3]Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1211-1221 (2007) - 2005
- [j2]Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong:
Power modeling and characteristics of field programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1712-1724 (2005) - [j1]Yan Lin, Fei Li, Lei He:
Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1035-1047 (2005) - [c14]Yan Lin, Fei Li, Lei He:
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC 2005: 645-650 - [c13]Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He:
Device and architecture co-optimization for FPGA power reduction. DAC 2005: 915-920 - [c12]Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak:
Scheduling of Soft Real-Time Systems for Context-Aware Applications. DATE 2005: 318-323 - [c11]Yan Lin, Fei Li, Lei He:
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA 2005: 199-207 - 2004
- [c10]Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy:
High-level area and power-up current estimation considering rich cell library. ASP-DAC 2004: 899-904 - [c9]Fei Li, Yan Lin, Lei He:
FPGA power reduction using configurable dual-Vdd. DAC 2004: 735-740 - [c8]Fei Li, Yan Lin, Lei He, Jason Cong:
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA 2004: 42-50 - [c7]Deming Chen, Jason Cong, Fei Li, Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117 - [c6]Fei Li, Yan Lin, Lei He:
Vdd programmability to reduce FPGA interconnect power. ICCAD 2004: 760-765 - 2003
- [c5]Fei Li, Deming Chen, Lei He, Jason Cong:
Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184 - [c4]Weiping Liao, Fei Li, Lei He:
Microarchitecture level power and thermal simulation considering temperature dependent leakage model. ISLPED 2003: 211-216 - [c3]Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy:
High Level Area and Current Estimation. PATMOS 2003: 259-268 - 2002
- [c2]Fei Li, Lei He, Kewal K. Saluja:
Estimation of Maximum Power-Up Current. ASP-DAC/VLSI Design 2002: 51- - 2001
- [c1]Fei Li, Lei He:
Maximum current estimation considering power gating. ISPD 2001: 106-111
Coauthor Index
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