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ORCIDYan Lin 0001
Person information
- affiliation: University of California, Los Angeles, Department of Electrical Engineering, CA, USA
Other persons with the same name
- Yan Lin — disambiguation page
- Yan Lin 0002
![[0000-0003-4419-9050]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-4419-9050")
— Beihang University, School of Automation, China (and 1 more) - Yan Lin 0003 — Jinan University, College of Cyber Security, Guangzhou, China (and 2 more)
- Yan Lin 0004 — Nanjing University of Science and Technology, School of Electronic and Optical Engineering, China (and 2 more)
- Yan Lin 0005 — Norwegian Institute for Water Research, Oslo, Norway (and 1 more)
- Yan Lin 0006 — Beijing Jiaotong University, China
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2010 – 2019
- 2012
[j8]Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He:
Statistical Timing and Power Optimization of Architecture and Device for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 5(2): 9:1-9:19 (2012)
2000 – 2009
- 2008
- [j7]Yu Hu, Yan Lin, Lei He, Tim Tuan:
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. 13(2): 30:1-30:29 (2008) - [j6]Yan Lin, Lei He, Mike Hutton:
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 124-133 (2008) - [c15]Lerong Cheng, Yan Lin, Lei He:
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA 2008: 159-168 - 2007
- [j5]Yan Lin, Mike Hutton, Lei He:
Statistical placement for FPGAs considering. IET Comput. Digit. Tech. 1(4): 267-275 (2007) - [j4]Fei Li, Yan Lin, Lei He:
Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 752-764 (2007) - [j3]Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1211-1221 (2007) - [c14]Yan Lin, Lei He:
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. DATE 2007: 636-641 - [c13]Yan Lin, Lei He:
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. FPGA 2007: 80-88 - [c12]Yan Lin, Lei He:
Device and architecture concurrent optimization for FPGA transient soft error rate. ICCAD 2007: 194-198 - 2006
- [j2]Yan Lin, Lei He:
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2023-2034 (2006) - [c11]Yu Hu, Yan Lin, Lei He, Tim Tuan:
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC 2006: 478-483 - [c10]Mike Hutton, Yan Lin, Lei He:
Placement and Timing for FPGAs Considering Variations. FPL 2006: 1-7 - [c9]Yan Lin, Yu Hu, Lei He, Vijay Raghunat:
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED 2006: 168-173 - 2005
- [j1]Yan Lin, Fei Li, Lei He:
Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1035-1047 (2005) - [c8]Yan Lin, Fei Li, Lei He:
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC 2005: 645-650 - [c7]Yan Lin, Lei He:
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. DAC 2005: 720-725 - [c6]Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He:
Device and architecture co-optimization for FPGA power reduction. DAC 2005: 915-920 - [c5]Yan Lin, Fei Li, Lei He:
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA 2005: 199-207 - [c4]Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He:
FPGA device and architecture evaluation considering process variations. ICCAD 2005: 19-24 - 2004
- [c3]Fei Li, Yan Lin, Lei He:
FPGA power reduction using configurable dual-Vdd. DAC 2004: 735-740 - [c2]Fei Li, Yan Lin, Lei He, Jason Cong:
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA 2004: 42-50 - [c1]Fei Li, Yan Lin, Lei He:
Vdd programmability to reduce FPGA interconnect power. ICCAD 2004: 760-765
Coauthor Index
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