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ORCIDRobert Rogenmoser
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2010 – 2019
- 2013
[j6]Robert Rogenmoser, Lawrence T. Clark:
Reducing Transistor Variability for High Performance Low Power Chips. IEEE Micro 33(2): 18-26 (2013)- [c5]Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama:
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. CICC 2013: 1-4 - [c4]Sang-Soo Lee, Edward Boling, Augustine Kuo, Robert Rogenmoser:
A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications. CICC 2013: 1-4 - 2012
- [c3]Robert Rogenmoser:
Reducing transistor variability for high performance low power chips. Hot Chips Symposium 2012: 1-19
2000 – 2009
- 2006
- [j5]Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou:
LVS verification across multiple power domains for a quad-core microprocessor. ACM Trans. Design Autom. Electr. Syst. 11(2): 490-500 (2006) - 2003
- [j4]Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu:
A 2× load/store pipe for a low-power 1-GHz embedded processor. IEEE J. Solid State Circuits 38(11): 1857-1865 (2003)
1990 – 1999
- 1997
- [j3]Robert Rogenmoser, Hubert Kaeslin:
The impact of transistor sizing on power efficiency in submicron CMOS circuits. IEEE J. Solid State Circuits 32(7): 1142-1145 (1997) - 1996
- [j2]Robert Rogenmoser, Qiuting Huang:
An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops. IEEE J. Solid State Circuits 31(3): 401-409 (1996) - [j1]Qiuting Huang, Robert Rogenmoser:
Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks. IEEE J. Solid State Circuits 31(3): 456-465 (1996) - [c2]Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle:
Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. PPSN 1996: 849-858 - 1994
- [c1]Qiuting Huang, Robert Rogenmoser:
A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications. ISCAS 1994: 11-14
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