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Journal Articles
- 2007
[j2]Kristof Denolf, Adrian Chirila-Rus, Paul R. Schumacher, Robert D. Turney, Kees A. Vissers, Diederik Verkest, Henk Corporaal:
A Systematic Approach to Design Low-Power Video Codec Cores. EURASIP J. Embed. Syst. 2007 (2007)- 2003
- [j1]Paul R. Schumacher:
An efficient JPEG2000 tier-1 coder hardware implementation for real-time video processing. IEEE Trans. Consumer Electron. 49(4): 780-786 (2003)
Conference and Workshop Papers
- 2005
- [c9]Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers:
Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs. FPL 2005: 391-396 - [c8]Paul R. Schumacher, Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Nick Fedele, Kees A. Vissers, Jan Bormans:
A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications. ICIP (2) 2005: 886-889 - [c7]Paul R. Schumacher, Marco Mattavelli, Adrian Chirila-Rus, Robert D. Turney:
A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs. ICME 2005: 872-875 - [c6]Paul R. Schumacher, Marco Mattavelli, Adrian Chirila-Rus, Robert D. Turney:
A Software/Hardware Platform for Rapid Prototyping of Video and Multimedia Designs. IWSOC 2005: 30-33 - [c5]Adrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers:
Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications. IEEE International Workshop on Rapid System Prototyping 2005: 246-249 - 2004
- [c4]Philip James-Roxby, Paul R. Schumacher, Charlie Ross:
A Single Program Multiple Data Parallel Processing Platform for FPGAs. FCCM 2004: 302-303 - 2003
- [c3]Massimo Ravasi, Marco Mattavelli, Paul R. Schumacher, Robert D. Turney:
High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder. PATMOS 2003: 440-450 - [c2]Paul R. Schumacher:
An efficient optimized JPEG 2000 tier-1 coder hardware implementation. VCIP 2003: 1089-1096 - 2002
- [c1]Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall:
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. ASAP 2002: 335-343
Coauthor Index
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