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ORCIDArindam Banerjee 0003
Person information
- affiliation: JIS College of Engineering, Kalyani, Nadia, West Bengal, India
Other persons with the same name
- Arindam Banerjee — disambiguation page
- Arindam Banerjee 0001 — University of Illinois Urbana-Champaign, USA (and 1 more)
- Arindam Banerjee 0002
![[0000-0002-1212-9704]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-1212-9704")
— Lehigh University, Department of Mechanical Engineering and Mechanics, Bethlehem, PA, USA
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2020 – today
- 2020
[j5]Arindam Banerjee, Debesh Kumar Das:
A Novel ALU Circuit based on Reversible Logic. J. Circuits Syst. Comput. 29(11): 2050172:1-2050172:17 (2020)
2010 – 2019
- 2019
- [c8]Arindam Banerjee, Debesh Kumar Das:
Arithmetic Circuits Using Reversible Logic: A Survey Report. ACSS (1) 2019: 99-110 - 2016
- [j4]Arindam Banerjee, Debesh Kumar Das:
A New Squarer design with reduced area and delay. IET Comput. Digit. Tech. 10(5): 205-214 (2016) - [c7]Arindam Banerjee, Debesh Kumar Das:
A new ALU architecture design using reversible logic. ISED 2016: 187-191 - [c6]Arindam Banerjee, Debesh Kumar Das:
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. VLSID 2016: 385-390 - 2015
- [j3]Arindam Banerjee, Debesh Kumar Das:
The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. J. Low Power Electron. 11(4): 467-478 (2015) - [c5]Arindam Banerjee, Debesh Kumar Das:
Squarer design with reduced area and delay. VDAT 2015: 1-6 - 2014
- [j2]Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat:
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8(1): 27-37 (2014) - [c4]Arindam Banerjee, Debesh Kumar Das:
Squaring in reversible logic using iterative structure. EWDTS 2014: 1-4 - 2013
- [c3]Arindam Banerjee, Debesh Kumar Das:
The Design of Reversible Multiplier Using Ancient Indian Mathematics. ISED 2013: 31-35 - 2012
- [c2]Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya:
Design of High Speed Vedic Multiplier for Decimal Number System. VDAT 2012: 79-88 - 2011
- [j1]Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya:
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. Microelectron. J. 42(12): 1343-1352 (2011) - [c1]Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat:
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. ISED 2011: 67-71
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