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ORCIDRanjani Parthasarathi
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2020 – today
- 2024
[j23]Shashikiran Venkatesha
, Ranjani Parthasarathi:
Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability. ACM Comput. Surv. 56(11): 275:1-275:76 (2024)- [c25]J. Dhurga Devi, Bama Srinivasan, Selvi Ravindran, Ranjani Parthasarathi, P. V. Ramakrishna, Lakshmanan Balasubramanian:
Machine Learning based Waveform Predictions using Discrete Wavelet Transform for Automated Verification of Analog and Mixed Signal Integrated Circuits. VLSID 2024: 61-66 - [i4]Bama Srinivasan, Mala Nehru, Ranjani Parthasarathi, Saswati Mukherjee, Jeena A Thankachan:
Automated Computer Program Evaluation and Projects - Our Experiences. CoRR abs/2404.04521 (2024) - 2023
- [c24]Dhanasekar V, Vinodhini Gunasekaran, Anusha Challa, Bama Srinivasan, J. Dhurga Devi, Selvi Ravindran, Ranjani Parthasarathi, P. V. Ramakrishna, Gopika Geetha Kumar, Venkateswaran Padmanabhan, Guha Lakshmanan, Lakshmanan Balasubramanian:
Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal Integrated Circuit Verification. ISQED 2023: 1-9 - [i3]Shashikiran Venkatesha, Ranjani Parthasarathi:
Enhancement in Reliability for Multi-core system consisting of One Instruction Cores. CoRR abs/2304.05072 (2023) - 2022
- [j22]Bama Srinivasan, Ranjani Parthasarathi:
A Formalism to Specify Unambiguous Instructions Inspired by Mīmāṁsā in Computational Settings. Logica Universalis 16(1-2): 27-55 (2022) - [i2]Shashikiran Venkatesha, Ranjani Parthasarathi:
A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems. CoRR abs/2203.07830 (2022) - 2021
- [j21]Padma Jayaraman, Ranjani Parthasarathi:
Performance counter based online pipeline bugs detection using machine learning techniques. Microprocess. Microsystems 84: 104262 (2021) - [i1]Shashikiran Venkatesha, Ranjani Parthasarathi:
A Survey of fault mitigation techniques for multi-core architectures. CoRR abs/2112.14952 (2021) - 2020
- [j20]Thanasekhar Balaiah, Ranjani Parthasarathi:
Autotuning of configuration for program execution in GPUs. Concurr. Comput. Pract. Exp. 32(9) (2020)
2010 – 2019
- 2019
- [j19]Balaji Jagan, Ranjani Parthasarathi, T. V. Geetha:
Bootstrapping of Semantic Relation Extraction for a Morphologically Rich Language: Semi-Supervised Learning of Semantic Relations. Int. J. Semantic Web Inf. Syst. 15(1): 119-149 (2019) - [c23]K. Kirutika, V. Vetri Selvi, Ranjani Parthasarathi, G. Subrahmanya V. R. K. Rao:
Controller Monitoring System In Software Defined Networks Using Random Forest Algorithm. ICCST 2019: 1-6 - 2017
- [j18]Bama Srinivasan, Ranjani Parthasarathi:
A survey of imperatives and action representation formalisms. Artif. Intell. Rev. 48(2): 263-297 (2017) - [j17]Thanasekhar Balaiah, Ranjani Parthasarathi:
Exploiting GPU memory hierarchy for accelerating a specialized stencil computation. Concurr. Comput. Pract. Exp. 29(21) (2017) - [j16]Padma Jayaraman, Ranjani Parthasarathi:
A Survey on Post-Silicon Functional Validation for Multicore Architectures. ACM Comput. Surv. 50(4): 61:1-61:30 (2017) - [j15]C. N. Subalalitha, Ranjani Parthasarathi:
Query Focused Summary Generation System using Unique Discourse Structure. Int. J. Inf. Retr. Res. 7(1): 49-69 (2017) - 2016
- [j14]Balaji Jagan, Ranjani Parthasarathi, T. V. Geetha:
Unsupervised learning of semantic relations of a morphologically rich language. Int. J. Inf. Commun. Technol. 8(4): 344-356 (2016) - [j13]Balaji Jagan, T. V. Geetha, Ranjani Parthasarathi:
Abstractive Summarization: A Hybrid Approach for the Compression of Semantic Graphs. Int. J. Semantic Web Inf. Syst. 12(2): 76-99 (2016) - 2015
- [j12]Chinnaudayar Navaneethakrishnan Subalalitha, Ranjani Parthasarathi:
Building a Language-Independent Discourse Parser using Universal Networking Language. Comput. Intell. 31(4): 593-618 (2015) - [c22]Ganesh J, Ranjani Parthasarathi, T. V. Geetha:
Automatic Construction of Tamil UNL Dictionary. MIKE 2015: 616-630 - 2014
- [j11]Balaji Jagan, T. V. Geetha, Ranjani Parthasarathi:
A Graph Based Query Focused Multi-Document Summarization. Int. J. Intell. Inf. Technol. 10(1): 16-41 (2014) - [j10]Chinnaudayar Navaneethakrishnan Subalalitha, Ranjani Parthasarathi:
A Unique Indexing Technique for Discourse Structures. J. Intell. Syst. 23(3): 231-243 (2014) - [j9]Balaji Jagan, T. V. Geetha, Ranjani Parthasarathi:
Graph-Based Bootstrapping for Coreference Resolution. J. Intell. Syst. 23(3): 293-310 (2014) - [c21]Jayabal Ganesh, Ranjani Parthasarathi, T. V. Geetha, Balaji Jagan:
Pattern Based Bootstrapping Technique for Tamil POS Tagging. MIKE 2014: 256-267 - 2013
- [j8]Bama Srinivasan, Ranjani Parthasarathi:
An intelligent task analysis approach for special education based on MIRA. J. Appl. Log. 11(1): 137-145 (2013) - 2012
- [j7]Bama Srinivasan, Ranjani Parthasarathi:
A Formalism for Action Representation Inspired by Mīmāṁsā. J. Intell. Syst. 21(1): 45-77 (2012) - [c20]Balaji Jagan, T. V. Geetha, Ranjani Parthasarathi:
Two-Stage Bootstrapping for Anaphora Resolution. COLING (Posters) 2012: 507-516 - [c19]Misiriya Shahul Hameed, C. N. Subalalitha, T. V. Geetha, Ranjani Parthasarathi:
A deconverter framework for Malayalam. ICACCI 2012: 847-856 - 2011
- [j6]D. Judia Salome, Ranjani Parthasarathi:
Mining ontological knowledge using Nyaya framework. Int. J. Netw. Virtual Organisations 8(1/2): 123-141 (2011) - [c18]Bama Srinivasan, Ranjani Parthasarathi:
Mimamsa Inspired Representation of Actions (MIRA). IICAI 2011: 498-517 - [c17]Balaji Jagan, T. V. Geetha, Ranjani Parthasarathi, Madhan Karky:
Anaphora Resolution in Tamil using Universal Networking Language. IICAI 2011: 1405-1415 - [c16]C. N. Subalalitha, Ranjani Parthasarathi:
A Language Independent Rhetorical Structure Framework Using Universal Networking Language. IICAI 2011: 1427-1440 - [c15]E. Umamaheswari, T. V. Geetha, Ranjani Parthasarathi, Madhan Karky:
A Multilevel UNL Concept based Searching and Ranking. WEBIST 2011: 282-289
2000 – 2009
- 2009
- [j5]A. P. Shanthi, Ranjani Parthasarathi:
Practical and scalable evolution of digital circuits. Appl. Soft Comput. 9(2): 618-624 (2009) - 2008
- [c14]Shri Vidhya Alagesan, Sruthi Kannan, G. Shanthi, A. P. Shanthi, Ranjani Parthasarathi:
Intrinsic Evolution of Large Digital Circuits Using a Modular Approach. AHS 2008: 19-26 - 2007
- [c13]T. K. S. Lakshmi Priya, V. Hari Prasad, D. Kannan, L. Karthik Singaram, G. Madhan, R. Meenakshi Sundaram, R. M. Prasad, Ranjani Parthasarathi:
Evaluating the Network Processor Architecture for Application-Awareness. COMSWARE 2007 - [c12]V. Vetri Selvi, Shakir Sharfraz, Ranjani Parthasarathi:
Mobile Ad Hoc Grid Using Trace Based Mobility Model. GPC 2007: 274-285 - [c11]T. K. S. Lakshmi Priya, Ranjani Parthasarathi:
An ASM Model for an Autonomous Network-Infrastructure Grid. ICNS 2007: 29 - [c10]V. Vetri Selvi, Ranjani Parthasarathi:
Trace Based Mobility Model for Ad Hoc Networks. WiMob 2007: 81 - 2005
- [j4]A. P. Shanthi, Ranjani Parthasarathi:
Genetic learning based fault tolerant models for digital systems. Appl. Soft Comput. 5(4): 357-371 (2005) - [c9]A. P. Shanthi, L. Karthik Singaram, Ranjani Parthasarathi:
Evolution of Asynchronous Sequential Circuits. Evolvable Hardware 2005: 93-96 - [c8]T. K. S. Lakshmi Priya, Ranjani Parthasarathi:
Architecture for an Active Network Infrastructure Grid - The iSEGrid . IWAN 2005: 38-52 - 2004
- [c7]A. P. Shanthi, P. Muruganandam, Ranjani Parthasarathi:
Enhancing the Development Based Evolution of Digital Circuits. Evolvable Hardware 2004: 91- - [c6]R. Sharmila, M. V. Lakshmi Priya, Ranjani Parthasarathi:
An Active Framework for a WLAN Access Point Using Intel's IXP1200 Network Processor. HiPC 2004: 71-80 - 2003
- [c5]Mohan G. Kabadi, Ranjani Parthasarathi:
Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem. Asia-Pacific Computer Systems Architecture Conference 2003: 337-351 - [c4]A. P. Shanthi, Ranjani Parthasarathi:
Exploring FPGA Structures for Evolving Fault Tolerant Hardware. Evolvable Hardware 2003: 184-191 - [c3]A. P. Shanthi, Balaji Vijayan, Manivel Rajendran, Senthilkumar Veluswami, Ranjani Parthasarathi:
JBits Based Fault Tolerant Framework for Evolvable Hardware. Engineering of Reconfigurable Systems and Algorithms 2003: 111-117 - 2002
- [c2]Mohan G. Kabadi, Natarajan Kannan, Palanidaran Chidambaram, Suriya Narayanan, M. Subramanian, Ranjani Parthasarathi:
Dead-Block Elimination in Cache: A Mechanism to Reduce I-cache Power Consumption in High Performance Microprocessors. HiPC 2002: 79-88 - 2001
- [c1]Ranjani Parthasarathi, Easwaran Raman, Karthik Sankaranarayanan, Lakshmi N. Chakrapani:
A Reconfigurable Co-Processor for Variable Long Precision Arithmetic Using Indian Algorithms. FCCM 2001: 71-80
1990 – 1999
- 1997
- [j3]Ranjani Parthasarathi, Ashok Jhunjhunwala:
Multiple precision square root using the Dwandwa square-root algorithm. J. Syst. Archit. 44(2): 143-158 (1997) - 1995
- [j2]Ranjani Parthasarathi, Ashok Jhunjhunwala:
Modified straight division: A computer implementation of multiple-precision division. Microprocess. Microprogramming 41(3): 193-209 (1995)
1980 – 1989
- 1989
- [j1]An-Chi Liu, Ranjani Parthasarathi:
Hardware monitoring of a multiprocessor system. IEEE Micro 9(5): 44-51 (1989)
Coauthor Index
aka: Chinnaudayar Navaneethakrishnan Subalalitha
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