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Yeonbok Lee
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2010 – 2019
- 2019
- [c9]Minwook Ahn, Seok Joong Hwang, Wonsub Kim, Seungrok Jung, Yeonbok Lee, Mookyoung Chung, Woohyung Lim, Young Joon Kim:
AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition. DATE 2019: 1495-1500 - 2018
- [c8]Jun Hyung Kim
, Jazzson Park, Minwook Ahn, Yeonbok Lee, Wonsub Kim, Hyung-Min Park:
Online Speech Dereverberation Using RLS-WPE Based on a Full Spatial Correlation Matrix Integrated in a Speech Enhancement System. IWAENC 2018: 36-40 - 2017
- [c7]Bernhard Egger, Hochan Lee, Duseok Kang, Mansureh S. Moghaddam, Youngchul Cho, Yeonbok Lee, Sukjin Kim, Soonhoi Ha, Kiyoung Choi:
A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures. CGO 2017: 197-209 - 2015
- [c6]Do Hyung Kim, Seokhwan Jo, Kiseok Kwon, Yeonbok Lee, Seungwon Lee, Young-Hwan Park, Sukjin Kim, Jaehyun Kim, Shihwa Lee:
Ultra-low-power voice trigger for wearable devices. ICCE-TW 2015: 76-77 - 2014
- [c5]Young-Hwan Park, Keshava Prasad, Yeonbok Lee, Kitaek Bae, Ho Yang:
Scalable radio processor architecture for modern wireless communications. FPT 2014: 310-313 - [c4]Ho Yang, Jaewook Shim, Jihoon Bang, Yeonbok Lee:
Software-based giga-bit WLAN platform. ICCE 2014: 478-479 - 2011
- [j1]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(7): 1519-1529 (2011) - [c3]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
On-chip dynamic signal sequence slicing for efficient post-silicon debugging. ASP-DAC 2011: 719-724 - 2010
- [c2]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. ICCD 2010: 402-408
2000 – 2009
- 2009
- [c1]Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
A Post-Silicon Debug Support Using High-Level Design Description. Asian Test Symposium 2009: 137-142
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