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Natsuki Kushiyama

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Journal Articles

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1999
[j2]
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  - journals/jssc/TakaseK99
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  - https://dblp.org/rec/journals/jssc/TakaseK99
Satoru Takase, Natsuki Kushiyama:
A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme. IEEE J. Solid State Circuits 34(11): 1600-1606 (1999)
1995
[j1]
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  - journals/jssc/KushiyamaTCLPMLCC95
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Natsuki Kushiyama, Charles Tan, Richard Clark, Jane Lin, Fred Perner, Lisa Martin, Mark Leonard, Gene Coussens, Kit Cham:
An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers. IEEE J. Solid State Circuits 30(11): 1286-1290 (1995)

Conference and Workshop Papers

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2009
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  - conf/isscc/HirabayashiKSTKSKFFNSKY09
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Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe:
A process-variation-tolerant dual-power-supply SRAM with 0.179µm² Cell in 40nm CMOS using level-programmable wordline driver. ISSCC 2009: 458-459

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