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Shien-Chun Luo

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Journal Articles

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2014
[j5]
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Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu:
A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1656-1665 (2014)
[j4]
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Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu:
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 947-951 (2014)
2013
[j3]
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Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu:
An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 677-681 (2013)
2010
[j2]
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Shien-Chun Luo, Lih-Yih Chiou:
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing. IEEE Trans. Circuits Syst. II Express Briefs 57-II(6): 440-445 (2010)
2009
[j1]
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Lih-Yih Chiou, Shien-Chun Luo:
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. IEEE Trans. Very Large Scale Integr. Syst. 17(11): 1659-1663 (2009)

Conference and Workshop Papers

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2022
[c8]
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Shien-Chun Luo, Kuo-Chiang Chang, Po-Wei Chen, Zhao-Hong Chen:
Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification. VLSI-DAT 2022: 1-4
2019
[c7]
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  - conf/vlsi-dat/Luo19
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Shien-Chun Luo:
Customization of a Deep Learning Accelerator. VLSI-DAT 2019: 1-2
2018
[c6]
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  - conf/vlsi-dat/ChangLHPC18
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Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, Yuan-Hua Chu:
MORAS: An energy-scalable system using adaptive voltage scaling. VLSI-DAT 2018: 1-4
2014
[c5]
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Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou:
An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS 2014: 2543-2546
[c4]
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Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou:
An ultra-low-power adaptive-body-bias control for subthreshold circuits. VLSI-DAT 2014: 1-4
2013
[c3]
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  - conf/isscc/LinCCCWSCLGCCCCSJIWW13
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Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159
2012
[c2]
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Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou:
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. ISCAS 2012: 2553-2556
2007
[c1]
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Lih-Yih Chiou, Shien-Chun Luo:
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. ISCAS 2007: 1157-1160

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