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Journal Articles
- 2012
[j8]Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao:
Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost. J. Low Power Electron. 8(1): 73-81 (2012)- 2011
- [j7]Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu:
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping. J. Electron. Test. 27(1): 43-56 (2011) - 2010
- [j6]Bin Zhou, Yizheng Ye, Zhao-lin Li, Jianwei Zhang, Xin-chun Wu, Rui Ke:
A test set embedding approach based on twisted-ring counter with few seeds. Integr. 43(1): 81-100 (2010) - [j5]Zhibo Zhou, Jinxiang Wang, Yizheng Ye:
Exact BER Analysis of Differential Chaos Shift Keying Communication System in Fading Channels. Wirel. Pers. Commun. 53(2): 299-310 (2010) - 2008
- [j4]Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye:
A Fully Integrated CMOS Active Bandpass Filter for Multiband RF Front-Ends. IEEE Trans. Circuits Syst. II Express Briefs 55-II(8): 718-722 (2008) - [j3]Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 677-682 (2008) - 2002
- [j2]Liyi Xiao, Yizheng Ye, Bin Li:
A New Synchronization Algorithm for VHDL-AMS Simulation. J. Comput. Sci. Technol. 17(1): 28-37 (2002) - 2000
- [j1]Liu Songyan, Zhigang Mao, Yizheng Ye:
Implementation of Java Card Virtual Machine. J. Comput. Sci. Technol. 15(6): 591-596 (2000)
Conference and Workshop Papers
- 2009
- [c25]Bin Zhou, Yizheng Ye, Xin-chun Wu, Zhao-lin Li:
Reduction of Test Power and Data Volume in BIST Scheme based on Scan Slice Overlapping. ISCAS 2009: 2737-2740 - [c24]Jianwei Zhang, Yizheng Ye, Bin-Da Liu, Feng Guan:
Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories. ISCAS 2009: 3070-3073 - [c23]Bin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke:
A new low power test pattern generator using a variable-length ring counter. ISQED 2009: 248-252 - 2008
- [c22]Qingli Zhang, Jinxiang Wang, Yizheng Ye:
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters. VLSI Design 2008: 377-382 - 2007
- [c21]Bin Zhou, Yizheng Ye, Yongsheng Wang:
Simultaneous reduction in test data volume and test time for TRC-reseeding. ACM Great Lakes Symposium on VLSI 2007: 49-54 - 2006
- [c20]Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories. APCCAS 2006: 1293-1296 - [c19]Qingli Zhang, Jinxiang Wang, Yizheng Ye:
Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses. APCCAS 2006: 1611-1614 - [c18]Tong Zhou, Zhibo Zhou, Mingyan Yu, Yizheng Ye:
Design of A Low Power High Entropy Chaos-Based Truly Random Number Generator. APCCAS 2006: 1955-1958 - [c17]Qingli Zhang, Jinxiang Wang, Yizheng Ye:
An energy-efficient temporal encoding circuit technique for on-chip high performance buses. ACM Great Lakes Symposium on VLSI 2006: 422-427 - [c16]Zhiqiang Gao, Mingyan Yu, Yizheng Ye, Jianguo Ma:
A CMOS bandpass filter with wide-tuning range for wireless applications. ISCAS 2006 - [c15]Guochi Huang, Tae-Sung Kim, Byung-Sung Kim, Mingyan Yu, Yizheng Ye:
Post linearization of CMOS LNA using double cascade FETs. ISCAS 2006 - [c14]Shengtian Sang, Xiaoming Li, Yizheng Ye:
Dependency driven partitioning objects generation for hardware/software partitioning. ISCAS 2006 - [c13]Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. ISLPED 2006: 135-138 - [c12]Tong Zhou, Mingyan Yu, Yizheng Ye:
A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor. VLSI Design 2006: 216-221 - 2005
- [c11]Yongsheng Wang, Jinxiang Wang, Fengchang Lai, Yizheng Ye:
Optimal Schemes for ADC BIST Based on Histogram. Asian Test Symposium 2005: 52-57 - [c10]Zhiqiang Gao, Jianguo Ma, Yizheng Ye, Mingyan Yu:
Large tuning band range of high frequency filter for wireless applications. ISCAS (1) 2005: 384-387 - [c9]Zhonghai Wang, Yizheng Ye:
The improvement for transaction level verification functional coverage. ISCAS (6) 2005: 5850-5853 - [c8]Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye:
A CMOS RF tuning wide-band bandpass filter for wireless applications. SoCC 2005: 79-80 - 2003
- [c7]Yongsheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye:
A Test Architecture for System-on-a-Chip. Asian Test Symposium 2003: 506 - 2002
- [c6]Yuxin You, Jinxiang Wang, Mingyan Yu, Yizheng Ye:
Design and implementation of concatenated decoder. DCV 2002: 135-142 - [c5]Xuemei Zhao, Yizheng Ye:
Design and Realization of a Low Power Register File Using Energy Model. PATMOS 2002: 268-277 - 2001
- [c4]Bin Li, Liyi Xiao, Yizheng Ye, Guoyong Huang:
CLUGGS and CLUCR-Two Matrix Solution Methods for General Circuit Simulation. Annual Simulation Symposium 2001: 78- - [c3]Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang:
A mixed-signal simulator for VHDL-AMS. ASP-DAC 2001: 287-292 - 1999
- [c2]Zulan Huang, Yizheng Ye, Zhigang Mao:
A New Algorithm for Retiming-Based Partial Scan. Asian Test Symposium 1999: 327- - 1998
- [c1]Pingying Zeng, Zhigang Mao, Yizheng Ye, Yuliang Deng:
Test Pattern Generation for Column Compression Multiplier. Asian Test Symposium 1998: 500-503
Coauthor Index
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