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ORCIDShai Rotem
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2010 – 2019
- 2010
[c7]Edson Borin, Youfeng Wu, Cheng Wang, Wei Liu, Maurício Breternitz Jr.
, Shiliang Hu, Esfir Natanzon, Shai Rotem, Roni Rosner:
TAO: two-level atomicity for dynamic binary optimizations. CGO 2010: 12-21
2000 – 2009
- 2003
- [j2]Ken S. Stevens, Ran Ginosar, Shai Rotem:
Relative timing [asynchronous design]. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 129-140 (2003) - 2002
- [c6]Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem:
Coordinated transformations for high-level synthesis of high performance microprocessor blocks. DAC 2002: 898-903 - 2001
- [j1]Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, Marly Roncken:
An asynchronous instruction length decoder. IEEE J. Solid State Circuits 36(2): 217-228 (2001) - 2000
- [c5]Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri:
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. ASYNC 2000: 62-72
1990 – 1999
- 1999
- [c4]Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun:
RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70 - [c3]Ken S. Stevens, Shai Rotem, Ran Ginosar:
Relative Timing. ASYNC 1999: 208-218 - [c2]Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken:
CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121 - 1998
- [c1]Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun:
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-
Coauthor Index
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