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Journal Articles
- 2017
[j5]Kai-Li Wang
, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test 34(3): 50-58 (2017)- [j4]Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers 66(8): 1293-1301 (2017) - 2016
- [j3]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test 33(2): 30-39 (2016) - [j2]Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers 65(3): 770-780 (2016) - 2011
- [j1]Mincent Lee, Li-Ming Denq, Cheng-Wen Wu:
A Memory Built-In Self-Repair Scheme Based on Configurable Spares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 919-929 (2011)
Conference and Workshop Papers
- 2022
- [c12]Pai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao:
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. VLSI-DAT 2022: 1-4 - 2020
- [c11]Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang:
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC 2020: 1-9 - [c10]Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen, Min-Jer Wang:
Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. ITC-Asia 2020: 1-6 - [c9]Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang:
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia 2020: 13-18 - 2019
- [c8]Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang:
High Quality Test Methodology for Highly Reliable Devices. ITC 2019: 1-6 - 2016
- [c7]Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC 2016: 58:1-58:6 - 2014
- [c6]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Redundancy architectures for channel-based 3D DRAM yield improvement. ITC 2014: 1-7 - [c5]Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen:
A novel DFT architecture for 3DIC test, diagnosis and repair. VLSI-DAT 2014: 1-4 - 2013
- [c4]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu:
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium 2013: 1-6 - 2012
- [c3]Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang:
A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC 2012: 1-9 - [c2]Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu:
Cost modeling and analysis for interposer-based three-dimensional IC. VTS 2012: 108-113 - [c1]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu:
A Memory Failure Pattern Analyzer for memory diagnosis and repair. VTS 2012: 234-239
Coauthor Index
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