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2010 – 2019
- 2014
[j9]Hoai-Huong Nguyen Le, Jongwoo Bae:
High-Throughput Parallel Architecture for H.265/HEVC Deblocking Filter. J. Inf. Sci. Eng. 30(2): 281-294 (2014)- 2013
- [j8]Jongwoo Bae:
Register array-based VLSI architecture of H.265/HEVC loop filter. IEICE Electron. Express 10(7): 20130161 (2013) - [j7]Jinsoo Cho, Jongkil Won, Jongwoo Bae:
Geometric Image Compensation Method for a Portable Projector Based on Rewarping Using 2D Homography. KSII Trans. Internet Inf. Syst. 7(9): 2299-2311 (2013) - [j6]Jongwoo Bae, Jinsoo Cho:
High-Performance VLSI Architecture of H.264/AVC CAVLD by Parallel Run_before Estimation Algorithm. J. Inf. Sci. Eng. 29(3): 595-605 (2013) - [c10]Nhat-Phuong Tran, Myungho Lee, Sugwon Hong, Jongwoo Bae:
Performance Optimization of Aho-Corasick Algorithm on a GPU. TrustCom/ISPA/IUCC 2013: 1143-1152 - 2011
- [j5]Jongwoo Bae, Jinsoo Cho, Baekhyun Kim, Jonghyen Baek:
High performance VLSI design of run_before for H.264/AVC CAVLD. IEICE Electron. Express 8(12): 950-955 (2011)
2000 – 2009
- 2009
- [c9]Myungho Lee, Jin-hong Jeon, Jongwoo Bae, Hyuk-Soo Jang:
Parallel implementation of a financial application on a GPU. ICIS 2009: 1136-1141 - 2008
- [j4]Jongwoo Bae, Jinsoo Cho:
A decoupled architecture for multi-format decoder. IEICE Electron. Express 5(18): 705-710 (2008) - [j3]Jinsoo Cho, Jongwoo Bae:
Color transient improvement with transient detection and variable length nonlinear filtering. IEEE Trans. Consumer Electron. 54(4): 1873-1879 (2008) - 2007
- [c8]Jongwoo Bae, Neungsoo Park, Seong-Won Lee:
Quarter-pel Interpolation Architecture in H.264/AVC Decoder. IPC 2007: 224-227 - 2006
- [j2]Jinsoo Cho, Jongwoo Bae:
Edge-adaptive local min/max nonlinear filter-based shoot suppression. IEEE Trans. Consumer Electron. 52(3): 1107-1111 (2006) - [c7]Jongwoo Bae, Neungsoo Park, Seong-Won Lee:
Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter. EUC 2006: 805-813
1990 – 1999
- 1998
- [j1]Jongwoo Bae, Viktor K. Prasanna:
Synthesis of area-efficient and high-throughput rate data format converters. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 697-706 (1998) - 1996
- [c6]Seonil Choi, Jongwoo Bae, Viktor K. Prasanna:
Synthesis of memory-based VLSI architectures for discrete wavelet transforms. EUSIPCO 1996: 1-4 - [c5]Neungsoo Park, Jongwoo Bae, Viktor K. Prasanna:
Synthesis of VLSI architectures for tree-structured image coding. ICIP (2) 1996: 999-1002 - 1995
- [c4]Jongwoo Bae, Viktor K. Prasanna:
Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms. ASAP 1995: 174- - [c3]Jongwoo Bae, Viktor K. Prasanna:
A fast and area-efficient VLSI architecture for embedded image coding. ICIP (3) 1995: 452-455 - 1994
- [c2]Jongwoo Bae, Viktor K. Prasanna, Heonchul Park:
Synthesis of a class of data format converters with specified delays. ASAP 1994: 283-294 - [c1]Jongwoo Bae, Viktor K. Prasanna:
A General Framework for Synthesis of Data Format Converters. ICPP (2) 1994: 197-200
Coauthor Index
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