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2010 – 2019
- 2018
[j4]Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi
, Toshio Goto, Takeo Kato, Masahiko Yoshimoto:
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]. IEICE Electron. Express 15(12): 20188003 (2018)- 2017
- [j3]Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto:
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video. IEICE Electron. Express 14(15): 20170668 (2017) - [c4]Yuri Nishizumi, Go Matsukawa, Koichi Kajihara, Taisuke Kodama, Shintaro Izumi, Hiroshi Kawaguchi, Chikako Nakanishi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto:
FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature. SiPS 2017: 1-6
1990 – 1999
- 1998
- [j2]Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya:
Software pipelining with path selection. Syst. Comput. Jpn. 29(9): 74-86 (1998) - 1996
- [c3]Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya:
Performance Comparison of ILP Machines with Cycle Time Evaluation. ISCA 1996: 213-224 - 1995
- [j1]Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya:
Code scheduling on a superscalar processor: SARCH. Syst. Comput. Jpn. 26(9): 13-22 (1995) - [c2]Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya:
Unconstrained Speculative Execution with Predicated State Buffering. ISCA 1995: 126-137 - 1993
- [c1]Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya:
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. ICCD 1993: 106-113
Coauthor Index
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