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ORCIDDavid G. Haigh
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2000 – 2009
- 2008
[j4]Yasuhiro Sugimoto, David G. Haigh:
A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2178-2187 (2008)- 2007
- [c18]Dafu Bai, David G. Haigh:
Derivation of power amplifier predistortion circuits by frequency to signal amplitude transformation. ECCTD 2007: 583-586 - 2006
- [j3]David G. Haigh, Thomas J. W. Clarke, Paul M. Radmore:
Symbolic Framework for Linear Active Circuits Based on Port Equivalence Using Limit Variables. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 2011-2024 (2006) - [j2]David G. Haigh, Paul M. Radmore:
Admittance Matrix Models for the Nullor Using Limit Variables and Their Application to Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(10): 2214-2223 (2006) - [j1]David G. Haigh:
A Method of Transformation from Symbolic Transfer Function to Active-RC Circuit by Admittance Matrix Expansion. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2715-2728 (2006) - [c17]David G. Haigh:
Analytic approach to or transformations for FET circuit synthesis. Part I. Nullator-norator tree transformations. ISCAS 2006 - [c16]David G. Haigh:
Analytic approach to or transformations for FET circuit synthesis. Part II. Nullator-norator re-pairing and cloning. ISCAS 2006 - [c15]David G. Haigh, Thomas J. W. Clarke, Paul M. Radmore:
A mathematical framework for active circuits based on port equivalence using limit variables. ISCAS 2006 - 2005
- [c14]David G. Haigh, Paul M. Radmore:
New admittance matrix descriptions for the nullor with application to circuit design. ECCTD 2005: 43-46 - [c13]David G. Haigh:
Systematic synthesis of operational amplifier circuits by admittance matrix expansion. ECCTD 2005: 115-118 - [c12]David G. Haigh, Paul M. Radmore:
Symbolic passive-RC circuit synthesis by admittance matrix expansion. ISCAS (1) 2005: 244-247 - [c11]David G. Haigh:
Symbolic active-RC circuit synthesis by admittance matrix expansion. ISCAS (1) 2005: 248-251 - [c10]Phil Corbishley, David G. Haigh:
Rules for systematic synthesis of all-transistor analogue circuits by admittance matrix expansion. ISCAS (6) 2005: 5966-5969 - 2004
- [c9]David G. Haigh, Paul M. Radmore:
Systematic synthesis method for analogue circuits. Part I. Notation and synthesis toolbox. ISCAS (1) 2004: 701-704
1990 – 1999
- 1995
- [c8]D. R. Webster, David G. Haigh, Anthony E. Parker:
Novel Circuit Synthesis Technique Using Short Channel GaAs Fets Giving Reduced Intermodulation Distortion. ISCAS 1995: 1348-1351 - [c7]T. L. Lim, David G. Haigh, D. R. Webster:
On the Design of Active GaAs Multipliers. ISCAS 1995: 1872-1875 - 1994
- [c6]D. R. Webster, David G. Haigh, Anthony E. Parker:
Distortion Compensation of Multi-Mesfet Circuits. ISCAS 1994: 189-192 - [c5]Carlos A. Losada, David G. Haigh:
On non-Linear Multi-FET Analysis. ISCAS 1994: 233-236 - [c4]D. R. Webster, Anthony E. Parker, David G. Haigh, Paul M. Radmore:
Device Circuit Interaction in the Common Source Amplifier. ISCAS 1994: 241-244 - [c3]R. Lecouls, David G. Haigh, Paul M. Radmore, D. R. Webster:
On Design of Analogue Multipliers using Gallium Arsenide MESFETs. ISCAS 1994: 677-680 - 1993
- [c2]Anthony E. Parker, David G. Haigh:
Compensation of 2nd Harmonic Distortion in a 4-FET Linearised Transconductor Circuit. ISCAS 1993: 1089-1092 - [c1]Carlos A. Losada, David G. Haigh, Paul M. Radmore:
A Systematic Method for Nonlinear Analysis of a Class of FET Circuits. ISCAS 1993: 2086-2089
Coauthor Index
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