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ORCIDKenneth P. Parker
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2010 – 2019
- 2012
[c30]Kenneth P. Parker:
Capacitive sensing testability in complex memory devices. ITC 2012: 1-6- 2011
- [c29]Kenneth P. Parker, Shuichi Kameyama, David Dubberke:
Surviving state disruptions caused by test: A case study. ITC 2011: 1-8 - 2010
- [c28]Xin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird:
Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing. ITC 2010: 467-476 - [c27]C. J. Clark, Dave Dubberke, Kenneth P. Parker, Bill Tuthill:
Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins. ITC 2010: 563-570 - [c26]Kenneth P. Parker:
Surviving state disruptions caused by test: The "Lobotomy Problem". ITC 2010: 571-578
2000 – 2009
- 2009
- [c25]Xin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird:
An outlier detection based approach for PCB testing. ITC 2009: 1-10 - [c24]Kenneth P. Parker, Jeff Burgess:
What is IEEE P1149.8.1 and why? ITC 2009: 1 - [c23]Steve Sunter, Kenneth P. Parker:
Testing bridges to nowhere - combining Boundary Scan and capacitive sensing. ITC 2009: 1-10 - 2008
- [c22]Dayton Norrgard, Kenneth P. Parker:
Augmenting Boundary-Scan Tests for Enhanced Defect Coverage. ITC 2008: 1-8 - [c21]Kenneth P. Parker, Neil G. Jacobson:
Boundary-Scan Testing of Power/Ground Pins. ITC 2008: 1-8 - 2007
- [c20]Kenneth P. Parker, Don DeMille:
A bead probe CAD strategy for in-circuit test. ITC 2007: 1-8 - [c19]Kenneth P. Parker, Stephen Hird:
Finding power/ground defects on connectors - a new approach. ITC 2007: 1-7 - 2005
- [c18]Kenneth P. Parker:
The effects of defects on high-speed boards. ITC 2005: 8 - [c17]Kenneth P. Parker:
Bead probes in practice. ITC 2005: 9 - [c16]Kenneth P. Parker:
A new probing technique for high-speed/high-density printed circuit boards. ITC 2005: 10 - 2004
- [c15]Kenneth P. Parker:
A New Probing Technique for High-Speed/High-Density Printed Circuit Boards. ITC 2004: 365-374 - [c14]Kenneth P. Parker:
Board Test Coverage Needs to be Standardized. ITC 2004: 1426 - 2003
- [j12]Kenneth P. Parker:
Testing for what? IEEE Des. Test Comput. 20(2): 96- (2003) - [j11]Bill Eklow, Carl Barnhart, Kenneth P. Parker:
IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks. IEEE Des. Test Comput. 20(5): 76-83 (2003) - [c13]Kenneth P. Parker:
Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes? ITC 2003: 1268-1276 - 2002
- [c12]Bill Eklow, Carl Barnhart, Kenneth P. Parker:
IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks. ITC 2002: 1056-1065 - [c11]Kathy Hird, Kenneth P. Parker, Bill Follis:
Test Coverage: What Does It Mean When a Board Test Passes?. ITC 2002: 1066-1074 - [c10]Kenneth P. Parker:
Board Test Is NOT Mature. ITC 2002: 1238 - 2001
- [c9]Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick:
Frequency detection-based boundary-scan testing of AC coupled nets. ITC 2001: 46-53 - 2000
- [c8]Kenneth P. Parker:
System issues in boundary-scan board test. ITC 2000: 724-728
1990 – 1999
- 1997
- [c7]Kenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa:
Design, Fabrications and Use of Mixed-Signal IC Testability Structures. ITC 1997: 489-498 - 1996
- [c6]Mick Tegethoff, Kenneth P. Parker, Ken Lee:
Opens Board Test Coverage: When is 99% Really 40%? ITC 1996: 333-339 - [c5]Kenneth P. Parker:
Introduction ITC 1996 Lecture Series on Unpowered Opens Testing. ITC 1996: 924 - 1995
- [j10]Mick Tegethoff, Kenneth P. Parker:
IEEE Std 1149.1: Where Are We? Where From Here? IEEE Des. Test Comput. 12(2): 53-59 (1995) - [c4]Kenneth P. Parker, David Greene:
The ITC Lecture Series: An Experiment. ITC 1995: 925 - 1994
- [c3]Kenneth P. Parker:
Observations on the 1149.x Family of Standards. ITC 1994: 1023 - 1993
- [c2]Kenneth P. Parker, John E. McDermid, Stig Oresjo:
Structure and Metrology for an Analog Testability Bus. ITC 1993: 309-322 - 1991
- [j9]Kenneth P. Parker, Stig Oresjo:
A language for describing boundary scan devices. J. Electron. Test. 2(1): 43-75 (1991) - 1990
- [c1]Kenneth P. Parker, Stig Oresjo:
A language for describing boundary-scan devices. ITC 1990: 222-234
1980 – 1989
- 1989
- [j8]Kenneth P. Parker:
The impact of boundary scan on board test. IEEE Des. Test 6(4): 18-30 (1989) - 1986
- [j7]Kenneth P. Parker:
Testability: Barriers to Acceptance. IEEE Des. Test 3(5): 11-15 (1986) - 1982
- [j6]Thomas W. Williams, Kenneth P. Parker:
Design for Testability - A Survey. IEEE Trans. Computers 31(1): 2-15 (1982)
1970 – 1979
- 1979
- [j5]Thomas W. Williams, Kenneth P. Parker:
Testing Logic Networks and Designing for Testability. Computer 12(10): 9-21 (1979) - 1978
- [j4]Edward J. McCluskey, Kenneth P. Parker, John J. Shedletsky:
Boolean Network Probabilities and Network Design. IEEE Trans. Computers 27(2): 187-189 (1978) - [j3]Kenneth P. Parker, Edward J. McCluskey:
Sequential Circuit Output Probabilities From Regular Expressions. IEEE Trans. Computers 27(3): 222-231 (1978) - 1975
- [j2]Kenneth P. Parker, Edward J. McCluskey:
Analysis of Logic Circuits with Faults Using Input Signal Probabilities. IEEE Trans. Computers 24(5): 573-578 (1975) - [j1]Kenneth P. Parker, Edward J. McCluskey:
Probabilistic Treatment of General Combinational Networks. IEEE Trans. Computers 24(6): 668-670 (1975)
Coauthor Index
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